Intel’s Ambitions to Lead in Advanced Packaging

September 21, 2023 / Ben Bajarin

At Intel Innovation, various announcements came out around Intel Foundry Services and Intel’s advanced packaging strategies. Below are our thoughts on what is significant and an overview of Intel packing offerings and a recap of recent news.

Why It’s Significant

While watchers will remain focused on Intel’s process technology execution, their initiatives in packaging are shaping up to be one of the most competitive in the industry.

Intel has several significant differentiators in their packaging toolkit that make it extremely likely they will get customers in the door for packaging even if they don’t win those customers for process technology.

Semiconductor design is transitioning from monolithic core designs to disaggregated designs (chiplets), allowing a more diverse silicon-on-package solution. As this inevitable shift occurs, Intel is well-positioned to compete with its diverse offerings in packaging technologies.

Key differentiators for Intel packaging technologies include the ability to mix and match tiles from any foundry (TSMC and Samsung currently do not do this), unique and proprietary inventions in to manage board warpage on large substrates, and thermal management.

Glass substrates could be key in Intel’s packaging differentiation. As the drive to larger die-size designs and larger systems in package solutions, organic substrates will run their course. Intel believes glass substrates are the answer and will allow for package sizes up to 240×240. Glass has distinct advantages to organic in thermal management. Glass also scales more efficiently of making the substrate smaller in density to handle the growing needs of more dense stacking of logic dies.

Intel believes we could see glass substrates toward the end of this decade and is in development now to work to scale this technology and make it cost-effective.

Ultimately, we believe packaging is a key differentiator for Intel Foundry Services but also for Intel product groups as well. Moving forward, we believe chiplet designs will become the norm for data center and edge network infrastructure solutions. This move to disaggregated design, or away from an SoC to a SiP (system in package) allows for numerous efficiency gains along with system design differentiation. It also allows for chip designers to be more intentional in the markets they are designing for and allows for more custom-level products without doing fully custom solutions for customers.

For IFS specifically, we believe advanced packaging solutions will attract a wide array of customers whether or not they choose to manufacture their products on Intel’s process technology.  That said, we believe getting these customers in the door is a key first step to begin to engage in customer relationships that can ultimately lead to more customers for Intel process technology with nodes like 20A and 18A specifically.

Overview of Intel Packaging Technologies

  • EMIB (Embedded Multi-die Interconnect Bridge): A technology that uses a small silicon bridge to connect two or more chips in a package, reducing the need for complex interposers and enabling higher bandwidth and lower power consumption. 
  • Foveros: A technology that stacks chips vertically using through-silicon vias (TSVs) and micro-bumps, allowing for heterogeneous integration of different types of chips, such as logic, memory, and I/O, in a 3D package. 
  • Co-EMIB: A technology that combines EMIB and Foveros to create packages that can integrate both horizontally and vertically connected chips, enabling more flexibility and scalability. 
  • OMNI (One Module with N Interconnects): A technology that uses a common interface to connect multiple chips in a package, regardless of their size, shape, or function, simplifying the design and manufacturing process. 
  • ODI (Omni-Directional Interconnect): A technology that uses large TSVs to connect the top die to the package substrate, reducing the number of micro-bumps and improving the signal integrity and power delivery. 
  • MDIO (Multi-Die I/O): A technology that uses a standard I/O interface to connect multiple chips in a package, enabling high-speed data transfer and compatibility with existing platforms. 


(New) Intel Announces Glass Substrate

  • Intel announced new glass substrates for advanced packaging to enable continued transistor scaling and advance Moore’s Law for future data centers and AI.
  • Compared to current organic substrates, glass offers higher interconnect density, better thermal/mechanical stability, and higher performance.
  • Glass substrates will enable a 10x increase in interconnect density versus organic substrates.
  • Initial use cases are large packages for data centers, AI, and graphics needing high speeds.
  • Benefits include higher transistor density (1 trillion by 2030), lower power, better yields, and flexibility for optical interconnects.
  • Intel has researched the reliability of glass substrates for over a decade and led previous packaging innovations.
  • Glass substrates will be introduced in the second half of this decade to meet future scaling needs beyond current organic substrate limits.


Details on Glass Substrate and Intel’s efforts to lead the industry

  • Intel has been developing glass substrate technology for over a decade, with significant investment in fabrication and R&D facilities in Chandler, AZ. This includes over $1 billion invested in a dedicated glass R&D line.
  • The shift to glass substrates is motivated by their superior electrical and mechanical properties compared to traditional organic substrates. Key advantages of glass core substrates:
  • Tunable modulus and coefficient of thermal expansion that can be matched closely to silicon. This enables larger panel sizes and improved dimensional stability.
  • Through-hole densities are approximately 10x higher than organic substrates. This enables more routing channels and connections for improved signaling.
  • Lower electrical loss, allowing higher speed signaling across the substrate. Glass has lower dielectric loss than organic materials.
  • Higher temperature capability up to over 300°C. This enables the integration of advanced power delivery networks and power devices directly into the substrate.
  • Intel’s test vehicles have demonstrated glass core substrates with three layers of redistribution layers (RDL) and high density through glass vias (TGV) with a 20:1 aspect ratio. The TGVs had a diameter of 75um in a 1mm thick glass core.
  • The glass panels support large form factors exceeding six reticle equivalents in area. This allows the integration of multiple high compute-density die-like GPUs and AI accelerators.
  • Intel has developed proprietary processes, materials, and equipment for the fabrication of glass core substrates. This includes over 600 patent inventions related to the glass substrate technology.
  • The glass substrates will be manufactured in Intel’s advanced CH8 facility in Chandler, AZ which has over 250 specialized tools for the development and production of glass and organic substrates.



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