Intel Foundry Technology Bets: A Full-Stack Strategy for the Disaggregated Era
The Disaggregated Era of Design
The semiconductor industry is entering a new phase. Progress is no longer measured by packing more transistors onto a single monolithic die. It is measured by how effectively systems are composed from smaller, specialized components. This is the disaggregated era of design. As Moore’s Law slows and the cost and complexity of large chips increase, chiplets—modular, functionally distinct pieces of silicon—are becoming the foundation of next-generation systems.
The chiplet approach provides new design freedom. Companies can optimize each tile for its role, such as AI acceleration, CPU, IO, memory, or analog, and then assemble them into tightly integrated, high-performance systems. This shift also places greater emphasis on system architecture. Power, thermal, bandwidth, and topology decisions now move to the center of silicon strategy.
Intel’s roadmap shows it is leaning into this transition. The company is positioning itself as the foundry built for the disaggregated era. Success in this model requires scalable interconnect, efficient power delivery, flexible packaging, competitive cost structures, and the ability to design large systems with modularity in mind. Intel is investing to deliver all of this in a unified stack.
This report evaluates Intel Foundry’s technologies and sets the stage for a broader series where we will dive deeper into the anchor technology bets shaping Intel’s positioning.
PowerVia and RibbonFET: Foundational Technologies
Intel will be the first foundry to introduce a fully integrated backside power delivery network (BSPDN) into high-volume manufacturing. PowerVia, coming in Intel 18A, separates power and signal paths by moving power delivery to the backside of the wafer. This provides measurable design benefits, including up to 4 percent performance uplift at iso-power and up to 10 percent improved utilization. Compared to Intel 3, Intel 18A delivers 15 percent better performance per watt and 1.3 times chip density.
Unlike partial solutions that shift only some power rails, PowerVia removes all power delivery from the front-side metal stack. This frees up area, reduces routing congestion, and improves design flexibility in dense logic. It also allows Intel to enable single-patterning of the lower metal layers, which reduces cost and manufacturing complexity.
A common assumption has been that backside power adds cost due to fabrication complexity. Intel’s 18A implementation challenges that assumption. Its cost model shows that the additional steps are offset by simplified front-side metal layers. By increasing minimum metal pitch from less than 25 nm to 32 nm, Intel enables direct-print single patterning and avoids the costly multi-patterning steps required in traditional flows. The result is that backside power delivery can be cost-neutral or better compared to conventional approaches.
RibbonFET, Intel’s gate-all-around (GAA) transistor, complements PowerVia. It provides stronger electrostatic control and higher drive current than FinFETs. Together, PowerVia and RibbonFET form the transistor and power foundation of Intel’s chiplet and packaging strategy.
Looking ahead, PowerVia continues beyond Intel 18A. Intel 14A introduces PowerDirect, a second-generation backside power architecture with more refined integration and design support. As adoption of chiplet-based systems increases, efficient backside power delivery becomes a critical enabler for scaling. PowerVia is positioned as a backbone for Intel’s future nodes.
These technologies matter because they address the core challenges of disaggregated design: routing density, power integrity, and physical partitioning. PowerVia decouples signal and power delivery, opening up new design options and improving thermal behavior. RibbonFET provides the control and scaling headroom needed for high-performance logic. For modular systems, these technologies are not optional. They are essential.
EMIB Scaling: Disaggregated at AI Scale
Intel continues to expand its EMIB (Embedded Multi-die Interconnect Bridge) technology, its modular 2.5D packaging platform. EMIB enables localized die-to-die interconnects without requiring full interposers. This approach avoids the cost and thermal penalties of large silicon interposers while still providing high-bandwidth, low-latency connections between chiplets.
The new EMIB-T variant integrates through-silicon vias (TSVs) and MIM capacitors, enabling stitched die-to-HBM4 connections and vertical power delivery. This is critical for high-bandwidth, low-noise memory access in AI workloads. Intel’s roadmap calls for EMIB-based systems with more than 12 times reticle-scale integration and over 24 HBM stacks by 2028.
EMIB’s value is not only in density. It also brings cost efficiency through small bridge structures and panel-based manufacturing. It reduces cycle time by avoiding chip-on-wafer steps. It provides a scalable, economically viable path for high-performance multi-tile designs.
Equally important, EMIB enables integration across foundries. Customers can combine dies from Intel and external foundries in one package without being locked into a single source. This provides dual sourcing options and design flexibility, which is particularly valuable for hyperscalers, defense, and AI infrastructure builders seeking supply chain resilience.
By supporting mixed-node and mixed-function integration—compute from one process, IO from another, memory from another—EMIB creates new flexibility in system design. It also provides Intel with a natural path to deepen customer engagement. Companies that start with EMIB packaging can later expand into Intel’s full stack of technologies.
Foveros Evolution: 3D Integration Options
Intel’s Foveros roadmap offers multiple stacking approaches. Foveros-S, R, and B deliver different options for bump pitches, redistribution layers, and substrate choices. This provides integration flexibility for compute, analog, or IO in systems where cost, density, or form factor vary by market.
Foveros Direct represents Intel’s true 3D platform. It uses hybrid bonding with pitches of 5 microns or less and bump densities of up to 10,000 per mm². This enables dense memory-on-logic stacking for inference or edge compute.
Used alongside EMIB, Foveros enables hybrid 2.5D/3D systems that balance cost, yield, and thermal design. Different dies can be stacked or bridged depending on function and system needs.
The strategic differentiator is flexibility. Foveros supports both incremental scaling and ambitious system integration without forcing a single model. Logic and memory can be co-located, analog or IO can be stacked below compute, and system form factors can be redefined. This flexibility is key for AI and HPC systems with tight power and thermal budgets.
Strategic Takeaway
Intel is aligning itself with the future of disaggregated computing. PowerVia resets the power delivery model. RibbonFET extends transistor scaling. EMIB and Foveros provide flexible packaging and integration paths. Co-packaged optics and related technologies extend bandwidth beyond the package.
These are not incremental updates. They are infrastructure-level moves designed to address the bottlenecks of a chiplet-based world. Together, they position Intel as a foundry partner for customers building modular systems that require fine-grained optimization across silicon, packaging, and interconnect.
The competitive conversation is shifting. This is not about mobile SoCs or monolithic scaling. It is about enabling AI, HPC, and hyperscale systems where composition defines competitiveness. Intel’s bet is clear: the most important compute systems of the future will be modular, and it is building its foundry offering to lead in that environment.